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- Manage IC packaging activity from concept thru development, qualification and HVM
- Actively participate, work with vendors and cross-functionally for technology risk analysis, mitigation plans, qualification timelines to ensure robust package quality, yield & reliability
- Direct interface with vendors (foundry, OSAT, substrate suppliers etc) to generate & maintain design integration documents, process flows, KPIs, risk registers, BOMs, DOEs, build trackers & action items
- Coordinate EFA/PFA activities, track yield/reliability pareto, data analysis & follow through issue resolution
- Generate internal & external presentations, technical reports for periodic engineering reviews
- BS/MS in Materials Science, Mechanical Engineering, Electrical Engineering or other semiconductor packaging related discipline
- 3+ yrs. experience with advanced microelectronics packaging, Fan out RDL, 2.5D, MCM, 3D, heterogeneous SIP and high performance build-up substrates,
- Deep understanding of MEOL/BEOL process integration, SPC, DOE, material trends, design rules capability for organic & ceramic flip chip package
- Hands on knowledge of package reliability requirements, industry standards such as JEDEC, IPC, failure analysis techniques, and interpretation of failure modes
- Experience collaborating with foundries, assembly service providers & subcontractor management is strongly preferred
- Strong problem solving, communication, organizational, interpersonal, and presentation skills