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RTL Design Engineer

Ottawa, Canada, Canada
Jul 14, 2020


Job Description




At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world’s first 5G networks, we empower the world’s builders and visionaries whose ideas solve every day problems and enhance people’s lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters – world class technology that improves the way we live and work. We are ONEXILINX.

Job Description

Xilinx is looking for a talented individual to join the Wired IP Solutions Group (WISG) in the position of Senior Design Engineer 1. The successful candidate will join our RTL design team developing ASIC and FPGA-based intellectual property (IP) to address the needs of state-of-the-art wired communications systems.

It is expected that the candidate will be experienced in Verilog RTL coding, and

front-end design flows. Working knowledge of test and verification strategies and processes would be an asset, as would experience with scripting languages such as Python, Perl and TCL. It would also be desirable for applicants to have experience with wired communications protocols, ASIC and FPGA architecture and design, and EDA design processes.


The successful candidate will have demonstrated their technical skill through prior experience delivering ASIC and/or FPGA solutions to the market, and leverage this experience to design and code innovative, high quality IP products.



In addition to strong technical abilities, the position requires excellent written and verbal communication skills that will be utilized for multi-location collaboration, and developing design specifications. A desire to mentor and coach junior engineers would be a plus.





Job Qualifications

  • BSEE minimum required.
  • +5 years digital design ASIC/FPGA experience
  • Extensive experience in ASIC/FPGA design and verification flows.
  • Familiarity with modern verification practices including System Verilog, UVM and assertion based test
  • Experience and knowledge of communications standards (such as Ethernet, Flex Ethernet, OTN, Interlaken)
  • Excellent written and verbal communication skills.


  • Expertise in System Verilog and VHDL
  • Experience designing digital communication systems (examples would include Ethernet, optical communications, and packet processing applications)
  • Experience with Xilinx tools and flow


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