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Xilinx is looking for a developer with expertise in modeling
complex HW architectures for fast simulation in SystemC TLM/C++.
As part of the Device Simulation Modeling team, the candidate will
be responsible for the definition, development, validation and release of
Verilog, VHDL, SystemVerilog or SystemC simulation models for all of Xilinx’s
All Programmable FPGAs, SoCs, 3D ICs and ACAP devices. Xilinx’s new hardware
programmable SoC FPGAs and Adaptive Compute Acceleration Platform (ACAP)
deliver most dynamic processor technology and are achieving record performances
in Data Center, Wireless/5G, Automotive/ADAS and Emulation applications. These
new applications and heterogeneous computing architecture brings in new
challenges in simulation modeling, especially in fast simulation of large scale
user designs that solve complex acceleration or AI/ML problems.
position requires strong programming fundamentals preferably in C++ and good
understanding of System On Chip (SoC) hardware architecture.
with simulation modeling in SystemC TLM, UVM, Verilog or System Verilog
with software development - preferably in C++
with hardware functional verification
- Experience in object-oriented design and programming
- Self-sufficient in software development concepts and methods, coding, and debugging
- Proactively identifies and delivers solutions that reduce development and support costs
- Capable of developing a single project in its entirety
- Demonstrates flexible adaptability in working with still maturing, generation-dependent software development and testing methods
Nice to have
to SoC performance analysis
SoC protocols, such as AMBA or PCI-express
RAM (DDR/HBM) controllers and memory bandwidth optimization
- Bachelors in EE/CE/CS with 3 years or Masters in EE/CE/CS with 1 year of relevant experience.