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Senior Mixed Signal Design Engineer

158686
San Jose, CA, United States
Jun 4, 2020

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world’s first 5G networks, we empower the world’s builders and visionaries whose ideas solve every day problems and enhance people’s lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters – world class technology that improves the way we live and work. We are ONEXILINX.

Job Description

  • Be part of the IP team of next generation PHY/PLL IPs

  • Participate in defining specification, testing and verification of the IP components. Contribute to micro-architecture specification for SOC/IP AMS blocks

  • Participate in Analog Mixed Signal IP Architecture specification reviews

  • Handle complete responsibility of an entire block starting from Micro-architecture specifications, schematic implementation, floor planning, and layout implementation and sign-off

  • Work with and Interact with layout, integration, verification and physical design teams 

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Job Qualifications


  • MS with 2+yrs exp in Electrical Engineering, Computer Science or related equivalent

  • Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm

  • Hands-on design experience in performance analog mixed signal circuit blocks such as, IO analog frontend, analog-to-digital (ADC), digital-to-analog (DAC) data converter, , LDO, biasing techniques, op-amps, interpolator circuits.

  • Experience with the following is a plus: Digital PLL techniques, TDC or DSP and control theory experience related to digital PLLs, Dual charge-pump PLL designs, Fractional-N PLLs, spread-spectrum PLLs.

  • Proficient with Cadence custom circuit design tools like ADE-L and ADE-XL and running Monte-Carlo, noise, aging, EM and IR drop simulations and stability analysis.

  • Experience in low power design techniques for high speed/custom digital circuit (e.g. CMOS/CML high speed design for counters, dividers, …) design and analysis including transistor level timing sign-off

  • Solid understanding of power, area and performance trade-offs in mixed signal IP design

  • Have good experience with simulation tools such as Spectre, Hspice, AFS, and MATLAB, System Verilog, Python.

  • Capable of understanding DRC and LVS results with verification tools (Calibre, ICV, or like)

  • Proficiency in scripting languages like Perl, Python, matlab etc. is a plus.

  • Able to work effectively in a team, with good interpersonal skills, enthusiasm and positive energy High-frequency design experience

  • Possess strong analytical/problem solving skills and pronounced attention to details

  • Must be a self-starter, and able to independently drive tasks to completion


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