Design Engineer - SGUnited Traineeship and Mid-Career Pathways Programme

Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX. 

This position is part of Singapore standard cell library design team, in close collaboration with the design automation (CAD) teams to develop and enhance the development and regression platforms.

The trainee’s main responsibilities are the design and development of advanced technology node standard cell libraries. These libraries contain both traditional and complex standard cells that significantly enhance implementation turnaround time while maintaining circuit performance with improved area/power trade-offs.

Cell based design/Place and Route methodology is playing a more significant role in our deep sub-micron designs, due to both design complexity and the challenges poised from the process technology.

The trainee will be working on multi disciplines, with a critical impact on getting functional products to market quickly.

The trainee is to be self-motivated to continuously develop skills and accept a variety of responsibilities as part of contributing to the design center’s success. Also, the trainee is to be able to communicate well and demonstrate a positive learning attitude.

Requirements 

SGUnited Traineeship Programme: Only Singaporeans/Singapore Permanent Residents fresh graduates from 2019/2020 with a Bachelor Degree in Electrical/Electronics/Computer Engineering

SGUnited Mid-Career Pathways Programme: Only Singaporeans/Singapore Permanent Residents with a Bachelor / Master's Degree in Electrical/Electronics/Computer Engineering

• Solid understanding of MOSFET electrical characteristics and experience with transistor level circuit simulators, such as HSPICE and SPECTRE.
• Understanding of layout at the transistor level in order to effectively work with the mask design team. Familiarity with reviewing DRC and LVS results is an added advantage.
• Understanding of and an ability to learn a wide variety of industry standard modeling formats including Liberty (CCS, ECSM, and NLDM), Verilog, LEF, Milkyway, SPICE.
• Experience in and a good understanding of standard cell architectures, including state retaining elements like latches and flops.
• Familiarity with working in the Linux environment, SKILL programming, load sharing concepts (such as LSF) and version control (such as ICManage) is a plus.

 Years of Experience

•  No experience required.

• SGUnited Traineeship Programme: 12 months
• SGUnited Mid-Career Pathways Programme: 9 months