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Xilinx Processing System SoC design group is looking for an SoC design engineer, who has an in depth technical experience of 7 years or more designing with ASIC/SOC design integration. The role expects the candidate to be versatile with Verilog, system Verilog, SoC design, timing closure, synchronization knowledge and chip product engineering concepts. A candidate who has experience with processing system (CPU based) and have designed or integrated blocks like ethernet/USB/GPU/Display port will be ideal match. The candidate must have done design hand-off to physical design team for the ASIC/SoC and should possess in depth knowledge on RTL quality checks(lint, cdc, timing constraints) and Static timing analysis.
The candidate should know the details of SoC integration done thru system Verilog interfaces, have basic knowledge of C/C++ language and robust digital VLSI design concepts.
The work involves understanding in depth of IP and subsystem, will be able to provide system level (SoC)solution for an architectural problem in discussion with Arch team. He/She should own a substem with more than 1 IP block and work for design completion, checklist closure, timing closure within the SoC program.
Education Requirements : Bachelor's of Engineering/Technology
Years of Experience: 7 years or more