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Senior SoC Design Engineer

158576
Hyderabad, India, India
May 20, 2020

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 Job Description:

 

Xilinx Processing System SoC design group is looking for an SoC design engineer, who has an in depth technical experience of 7 years or more designing with ASIC/SOC design integration. The role expects the candidate to be versatile with Verilog, system Verilog,  SoC design, timing closure, synchronization knowledge and chip product engineering concepts. A candidate who has experience with processing system (CPU based) and have designed or integrated blocks like ethernet/USB/GPU/Display port will be ideal match. The candidate must have done design hand-off to physical design team for the ASIC/SoC and should possess in depth knowledge on RTL quality checks(lint, cdc, timing constraints) and Static timing analysis.

The candidate should know the details of SoC integration done thru system Verilog interfaces, have basic knowledge of C/C++ language and robust digital VLSI design concepts.  

 

The work involves understanding in depth of IP and subsystem, will be able to provide system level (SoC)solution for an architectural problem in discussion with Arch team. He/She should own a substem with more than 1 IP block and work for design completion, checklist closure, timing closure within the SoC program.

Education Requirements : Bachelor's of Engineering/Technology

Years of Experience: 7 years or more

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