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The ideal candidate should have proven taking chips to production with experience in one or more of the following areas: DDR/SerDes IO transmitter and receiver front end circuit architecture, Dual charge-pump PLL designs, Fractional-N PLLs, spread-spectrum PLLs, Digital PLL/DLL techniques, etc. High speed digital circuit design and analysis (e.g., STA, formal verification). Digitally assisted analog circuit and techniques. Good knowledge of band gaps, bias, op-amps, LDOs, feedback and compensation techniques. Experience in VCO design including but not limited to LC VCOs. Lab and ATE test plans and measurement for characterization, and volume production.
- Definition, review and sign-off on IP top level and component level specifications
- AMS components circuit and layout design
- Supervise pre-silicon layout, post-silicon characterization and debug.
- Support product bring-up and debug , and Sign-off on test-plans and characterization reports.
- Interface with SOC teams, system HW/SW teams, and global manufacturing teams
- Creating silicon and system level specifications
- Presenting design trade-off analysis and implementation recommendations with custom circuit designers
- Behavioral modeling of different blocks in transceivers (PLL, DLLs, FFE, CTLE, DFE, CDR, PLL, etc.)
- Knowledge of Adaptive signal processing algorithms for equalization adaptation desirable
- Developing and verifying IO/SerDes design models
- BS with 8+ yrs exp or MS with 6+ yrs exp of PHD with 3+ yrs of experience in Electrical Engineering, Computer Science or related equivalent
- Experience in high speed serial and/or parallel mixed signal PHY/IO designs
- Strong fundamentals and knowledge of mixed signal circuit architecture and design techniques for receiver/transmitter and PLL/DLL/clocking.
- Hand-on design experience in multi-Gbps serial (PCIE, USB, …), parallel high BW memory interface PHY/IOs (DDR4/DDR5, HBM2/HBM3, gDDR5/gDDR6, …) and chip-to-chip links PHY IPs owning
- Experience in mixed signal design circuit blocks such as digital/analog DLLs, duty cycle corrector, clock and data recovery, clock mixer, …
- Experience in low power design techniques for high speed/custom digital circuit (e.g. CMOS/CML high speed design for counters, dividers, …) design and analysis including transistor level timing sign-off
- Solid understanding of power, area and performance trade-offs in mixed signal IP design
- Design Experience in FinFet advanced CMOS process nodes 16nm/7nm and below coupled with a solid understanding of transistor device performance and fundamentals
- Proficient in AMS design flows, tools, and methodologies. Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools
- Work with project-manager, system architects, IC designers and physical designers to guarantee quality/timely deliverables meeting project’s schedule and technical requirements
- Track record of successfully taking designs to production
- Excellent written and verbal communication skills able to operate without direct supervision but also work cross-functionally, cross-geographies collaborating and being part of a multi-disciplinary team in a dynamic/fast paste environment.
- Exhibit strong initiative and ownership of tasks and responsibilities. Seek help proactively as well as share and pass on knowledge