At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.
Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.
If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.
Be part of Xilinx's IP team responsible for R&D/design of next generation clocking/PLLs solutions, next generation IOs, high speed memory (LPDDR4/DDR4, LPDDR5/DDR5, gDDR6, HBM2/HBM3, …), chip-to-chip Gbps proprietary PHY IP solutions. Responsibilities include but not limited to:
1. Be part of the IP team of next generation PHY/PLL IPs. Engage in design architecture to micro-architecture phase
2. Participate in defining specification, testing and verification of the IP components.
3. Perform RTL-level design, including micro-architectural definition, of the digital portions of the IP architecture
4. Work closely with methodology, PD teams to implement RTL design into GDSII.
5. Drive design closure thru synthesis, static-timing analysis, logical equivalency checking. Help improve flows and scripts for such tasks
6. Support post-silicon product bring-up and debug, and sign-off on test-plans and characterization reports.
7. Design support for SOC/FPGA integration teams, system HW/SW teams, and global operations/manufacturing teams.
8. Setup and analysis of lint, synthesis, timing closure and DFT coverage reports
9. Define or participate in micro-architecture definition and drive for power, performance and area (PPA) targets/enhancements
10. Influence the methodology on mixed signal IP flows on simulations, timing closure. Participate in establishing CAD and design methodologies for correct by construction designs.
11. Support SOC/FPGA integration activities