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IC Layout Engineer

158466
Singapore, Singapore, Singapore
Jul 22, 2020

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.


Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.


If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.


Xilinx is looking for talented individual/s to join the global team as IC Layout Design Engineer (various positions available). Successful candidates will work as part of an experienced team executing projects in advanced CMOS manufacturing processes, 16nm or smaller.


Layout is extremely challenging at these smaller process nodes. There is the opportunity to contribute to methodology initiatives to accelerate design layout.


Job Description:

  • Layout design support (remote or on-site) for various analog mixed signal design groups such as memory array, IO, PLL, SerDes, clocking and etc.
  • Responsible for in-house standard library/IP cell layout developments
  • Collaborate with the circuit design teams to constantly optimize layout implementation for better power, performance and area
  • Layout verifications closure per foundry and internal rules
  • Conduct layout signoff review meeting
  • Take initiative to improve tools and way of working


The successful incumbent should be/possess the following:

  • Entry-Level Graduates with Master’s/Bachelor’s Degree in Electrical/Electronic Engineering or equivalent
  • Preferably with 2-3 years of analog custom IC layout design experience in deep sub-micron process node (16nm and below), 7nm would be advantage.
  • Solid Understanding in schematic-driven layout, floor planning, placement, routing and layout verifications.
  • Hands-on experience in using Cadence and Mentor tools is preferred
  • Strong debug capabilities with parasitic extraction, LVS/DRC and other physical verification checks.
  • Sound knowledge of device matching, pitch matching and array matching
  • Strong understanding of deep sub-micron layout design related challenges (including parasitic impact) and good understanding of DFM guidelines.
  • Good handle on IR/EM related issues in analog mixed signal layouts
  • Familiarity with circuit design concepts, flow and IC manufacturing processes
  • Understanding of digital SOC flow is an advantage.
  • Knowledge of scripting languages like SKILL, PERL, TCL etc. is a plus
  • Capacity to tackle board innovative approaches and working methods
  • Strong communication, documentation and presentation skills.
  • Highly motivated, excellent teammate and customer oriented.
  • Ability to work across functions, level and with remote design teams
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