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Being part of the Xilinx Packaging Development department, you will work with an engineering team to assess and validate electrical performance for the new cutting-edge packaging technology and industry-leading ACAP products in the die/pkg/board co-design environment. You will also manage the new product/package introduction by teaming up with internally the package architecture and design team and externally the silicon partners, signal/power integrity, program management, and the operating organization. This position requires both technical insight and skillful communication to develop the multi-functional alignment to resolve issues during the execution of new product development.
Oversee definition, design, verification, and documentation for Xilinx FPGA development and package design architecture and matrix definition. Determines architecture design, logic design, and system simulation. Package design architect responsible to new product family and package matrix definition,
performance and cost tradeoff assessment, technology and design rule development, package structure planning. Drive integration, verification and characterization in advanced FPGA systems, incorporating
silicon/TSV, package stack-up/routing/PDN, discrete decoupling capacitors and system board interfaces. Utilize techniques in EM (Electromagnetic) and Circuit model generation, simulation, and validation for correlating hardware measurements versus pre/post-layout simulation, effecting a signal integrity driven design flow for advanced FPGA product development. Optimize system level performance in areas including power integrity, high speed IO/SSO, and multi-tens gigabit transceivers. Drive cost reduction through adoption of leading edge package technology while achieving performance driven objectives. Technical lead in Xilinx package development department.
• Possesses an understanding of high-speed serdes, memory interface, supply voltage noise, and packaging technologies/trend to drive package design validation throughout all phases of product cycle
• Understand in-depth package development flow and work fluently with NPI program management and manufacturing/process team to synthesize a cohesive package introduction plan
• Interface and negotiate effectively across engineering teams to balance performance adequacy and schedule commitment
• Drive package design review, manage modeling/simulation projects, prepare and present the final design review (FDR) to all product partners
• Collaborate with silicon IP, silicon evaluation and package technology teams to establish the development plan and timeline for the R&D project, test vehicle, and prototype packages
Education Requirements and Years of Experience:
BS with 12+ years of exp or MS with 8+ years of exp or PhD with 5+ years of exp in Electrical Engineering or Computer Engineering or related equivalent
Industry experience in IC package technology and product development in the semiconductor industry with consistent track record. 5+ years project/program execution and management experience in the IC package development field Demonstrate technical leadership in complex product development under challenging technical and schedule conditions
1. FPGA package matrix definition for advanced 16nm and 7nm technology nodes including family migration, and cost-performance-reliability (electro-migration and TDDB) trade-off.
2. Designing large FPGA flip chip BGA devices (>4000 pins) from product definition, die floor planning, package architecture and die-package co-designs.
3. High speed, RF, microwave designs, circuit/package modeling and system level simulation for data rate of 56Gbps NRZ and 112Gbps PAM4.
4. EM tools and debugging skills including Ansoft HFSS, Cadence/Sigrity PowerSI/Speed2000/XcitePI, HSPICE/ADS system simulator, Cadence APD, Matlab/Python, and scripting language.
5. Physical layout skills for up to 18 layers and 4072 BGA pins.
6. Advanced thin-core and INFO package design.