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Senior Design Engineer 2

158224
Hyderabad, India, India
Dec 23, 2019

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.


Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), it has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas tackle everyday problems and improve people's lives.


If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about crafting meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world-class technology that improves the way we live and work. We are ONEXILINX.


As part of the full-chip integration team, the candidate will be involved in different phases of Fullchip physical integration as well as Physical implementation of sub-blocks from RTL to delivery of final GDSII.


Job Requirements:

  1. Master’s/Bachelor’s degree in Electrical/Electronics Engineering with 6 to 12 years of experience in semi-custom or PNR design
  2. Expertise in the physical implementation of digital blocks using industry-standard Automatic Palace and Route (APR) Tools meeting PPA spec
  3. Expertise in floor planning including power grid design to meet EMIR specifications
  4. Excellent understanding of timing concepts
  5. Hands-on experience in Generating and Implementing ECOs to fix timing, noise and EMIR violations
  6. Good hands-on experience in analyzing and fixing physical DRCs and analyzing LVS issues in Calibre tool
  7. Participate and contribute to improving physical design methodologies and flows
  8. Excellent scripting skills in Tcl/Perl and scripting savvy
  9. A good understanding of electrical, timing and reliability issues in deep sub-micron circuit design
  10. Strong Debug skills
  11. Must be a phenomenal teammate
  12. Must be having good oral and written communication skills
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