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We have an opening for a Sr Design Engineer in the SoC Timing Closure team. This team is designing and analyzing the future generations high-performance FPGA that is combined with CPU and IO subsystems to give unparalleled flexibility to FPGA consumers.
As a member of SoC Design and Integration team, you will:
Common Essentials Duties include:
Creates and tracks schedules to ensure that component deliveries achieve technical and quality objectives per specifications
Becomes in-house expert in tools and methodologies for block and chip level timing closure