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Senior Design Engineer 1

158118
Hyderabad, India, India
Dec 11, 2019

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

 Circuit design in IO / Analog (PHY) area:


Be part of Xilinx’s analog/mixed signal IP design team responsible for the design and development of next generation IOs, high speed memory (LPDDR5, DDR5, gDDR6, HBM2/HBM3) and chip-to-chip Gbps proprietary PHY IP solutions.


The candidate will be involved in

  1. design and implementation of AMS components in 16nm/7nm and beyond.
  2. feasibility study of new architectures, implementing and verifying functionality/performance of designs
  3. pre-and-post Silicon characterization and debug
  4. working closely with SOC, SW, CAD and PM teams in implementing designs using custom/structured-custom flows.

Requirements for this position include:

  1. 2-6yrs experience in high speed serial and/or parallel mixed signal PHY/IO designs.
  2. Strong fundamentals and knowledge of mixed signal circuit architecture and design techniques for receiver/transmitter and PLL/DLL/clocking.
  3. Hands on experience in multi-Gbps serial (PCIE, USB, …), parallel high BW memory interface PHY/IOs (DDR4/DDR5, HBM2/HBM3, gDDR5/gDDR6, …) and chip-to-chip links PHY IPs
  4. Experience in mixed signal design circuit blocks such as digital/analog DLLs, duty cycle corrector, clock and data recovery, clock mixer, …
  5. Solid understanding of power, area and performance trade-offs in mixed signal IP design
  6. Proficient in AMS design flows, tools, and methodologies. Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools
  7. Strong experience working with layout designers in understanding design/technology/layout constraints.
  8. Knowledge of physical design flows, timing closure expertise desired.
  9. Excellent written and verbal communication skills especially cross geographic interaction with overseas teams.
  10. Exhibit strong initiative and ownership of tasks and responsibilities with an open mind to contribute to any area/project.

Education Requirements M Tech or equivalent

Years of Experience 2 to 6years

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