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Circuit design in IO / Analog (PHY) area:
part of Xilinx’s analog/mixed signal IP design team responsible for the design
and development of next generation IOs, high speed memory (LPDDR5, DDR5, gDDR6,
HBM2/HBM3) and chip-to-chip Gbps proprietary PHY IP solutions.
The candidate will be involved in
- design and implementation of AMS components in 16nm/7nm
- feasibility study of new architectures, implementing
and verifying functionality/performance of designs
- pre-and-post Silicon characterization and debug
- working closely with SOC, SW, CAD and PM teams in
implementing designs using custom/structured-custom flows.
for this position include:
- 2-6yrs experience in high speed serial and/or parallel
mixed signal PHY/IO designs.
- Strong fundamentals and knowledge of mixed signal
circuit architecture and design techniques for receiver/transmitter and
- Hands on experience in multi-Gbps serial (PCIE, USB,
…), parallel high BW memory interface PHY/IOs (DDR4/DDR5, HBM2/HBM3,
gDDR5/gDDR6, …) and chip-to-chip links PHY IPs
- Experience in mixed signal design circuit blocks such
as digital/analog DLLs, duty cycle corrector, clock and data recovery,
clock mixer, …
- Solid understanding of power, area and performance
trade-offs in mixed signal IP design
- Proficient in AMS design flows, tools, and
methodologies. Familiar with Cadence schematic capture, virtuoso, Spectre
and/or HSPICE circuit simulation tools
- Strong experience working with layout designers in
understanding design/technology/layout constraints.
- Knowledge of physical design flows, timing closure
- Excellent written and verbal communication skills
especially cross geographic interaction with overseas teams.
- Exhibit strong initiative and ownership of tasks and
responsibilities with an open mind to contribute to any area/project.
M Tech or equivalent
Years of Experience 2 to 6years