Description About Xilinx
At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.
Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.
If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.
The Data Center Group (DCG) is forming a new team and we are looking for several talented RTL and Verification engineers. You will be part of the team developing networking applications and solutions, join us and be a part of the Xilinx ‘data center first’ strategy in the newly formed Data Center Group!
The role involves work on all aspects of the FPGA design flow including architectural specification, test planning, RTL design, RTL verification, through synthesis and implementation to hardware and lab validation.
Job Responsibilities and Skills
- Works within a team to define innovative new products and ability to deliver high quality, complex projects on time
- Experienced in digital design and verification techniques and flows
- RTL level design in Verilog / System Verilog
- RTL level verification in System Verilog / UVM
- Use of implementation tools, timing analysis, scripting (TCL/Python/Perl, etc), Linux
- Problem solving and debugging skills
- Ability to communicate technical information in an organized and comprehensible manner
Degree in Electrical Engineering, Computer Engineering, Computer Science or related equivalent. MS or BS with minimum of 2 years of relevant work experience.
Experience with Vivado Design Suite, FPGA design flow, RTL simulation, PCIe, Ethernet desirable.