UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Senior Design Engineer 2

157991
Hyderabad, India, India
Dec 4, 2019

Share:

Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.


JOB DESCRIPTION:

• Executing Static timing analysis of  hierarchical designs at top level
• Debug timing constraint issues, make edits to fix them
• Debug timing QOR issues in primetime
• Timing, Noise ECO creation using PT ECO, Tweaker , SMVA, Hyperscale
• Create automation scripts to extract timing data generation using Perl/TCL
• Understand and analyze  primetime reports - check_timing, analysis_coverage, report_qor, report_constraints,


JOB REQUIREMENTS:
• Should be hands on STA Flow experience 
• Good flow understanding.
• Must have strong debugging skills- timing issues, SDC , clock propogation
• Must Worked on multiple tapeout timing closure at full chip



Education Requirements BE / MS in EE 

Years of Experience 5+
Share:
 

Similar Jobs

Senior Staff Technical Writer

Hyderabad, India, India

Software Engineer-2

Hyderabad, India, India

Senior Design Verification Engineer 2

Hyderabad, India, India

Senior Design Verification Engineer-1

Hyderabad, India, India

Senior Technical Writer

Hyderabad, India, India

Design Services Engineering Manager

Hyderabad, India, India

Devops Software Engineer

Hyderabad, India, India

System Performance Architect

Hyderabad, India, India

IP Design Engineer (Contractor)

Hyderabad, India, India

CAD Infrastructure DevOps Engineer

Hyderabad, India, India

Staff Design Engineer

Hyderabad, India, India