Xilinx FPGA Architecture team seeks experienced professionals with Masters/ Bachelors in EE /EC/CS and 8+ years of experience in EDA tool development using C++. Experience in Placer/Router/Synthesis/Timer/Power estimator development is desired. The candidate should have an inclination for research-oriented work.
At Architecture team we model next generation FPGAs and evaluate it to measure the improvement in power, performance and area to be had, when compared to previous FPGA generations. For above activity we enhance placer and router, for it to support placement and routing on proposed architecture. We develop software tools that employs various mathematical methods (SAT/ILP) to understand and improve limitations of future architecture. We implement complex user designs on proposed architecture to foresee possible timing and routing challenges. Learnings from this goes into improving the architecture.
Overall the team’s activities broadly are modeling future FPGAs, enhancing software that implements designs on FPGA, developing software tools and techniques to measure FPGA performance and identify performance bottlenecks. These activities should lead to improvements in Xilinx’s future architecture.
Working in this group enables a candidate to get deep understanding Xilinx’s FPGA Architecture internals on the other hand it provides them with an opportunity to enhance existing or develop prototype Placer, Router (Signal and clock), Power estimator
Education Requirements Masters/ Bachelors in EE /EC/CS