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SerDes Architecture and Modeling Engineer

San Jose, CA, United States
Oct 23, 2019


Job Description


At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.


Job Description:



The SerDes Architecture and Modeling Group has responsibilities in generating robust SerDes architecture and algorithms, creating silicon and system level specifications, developing and verifying SerDes design models, developing IBIS-AMI models for system level simulations and for customers, evaluating system performance margin trade-offs, analyzing system SI and PI, and bringing up and characterizing silicon.


We’re looking for a system architect to join a fast paced transceiver design team. Our team stays ahead of the technology curve to deliver world-class programmable transceiver solutions for multiple FPGA platforms, supporting over 20 protocols with thousands of customer applications.


The successful candidate will be analytical, thorough, self-driven, and have an excellent track record in the following areas:


  • Signal processing, data coding, and FEC algorithms

  • SerDes architecture development including equalizers and time recovery for NRZ and PAM4 systems

  • Behavioral modeling of different blocks in transceivers

  • Familiarity with optical link analysis and evaluation is a plus

  • Presenting design trade-off analyses and implementation recommendations with custom circuit designers





Job Requirements:


  • BS with 3+ years of exp. or MS with 1+ year of exp in Electrical Engineering, Computer Engineering or Related Equivalent 

  • Signal modulation, coding, and FEC knowledge and experience

  • Architecture experience with transceiver equalizers (TX FIR, RX analog FFE, CTLE, and DFE) – DSP (FFE and DFE) experience is preferred

  • Architecture experience with transceiver timing recovery, such as high speed PLLs, CDRs, etc.

  • ADC based SerDes architecture experience is a plus

  • Experience with using and developing transceiver modeling, analysis, and characterization tools – IBIS-AMI model development experience is a plus and familiarity with Simulink/Matlab and C/C++ programming

  • Experience with lab equipment for high-speed digital systems

  • Good understanding of high speed signal integrity issues

  • Excellent technical communication skills (presentations and documentation)

  • Team player









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