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Senior Staff Design Engineer

157800
San Jose, CA, United States
Oct 22, 2019

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

Responsibilities

 

  • Front-end design of a next generation massively parallel DSP/ML architecture
  • Work with Architecture, physical design, verification and software teams to play a major role in the silicon implementation
  • Develop specification of the micro-architecture
  • Analyze performance, power and area tradeoffs, and make implementation choices
  • Work with Architecture and Software teams to ensure micro-architecture and design is fully verified/validated across multiple platforms
  • Solve customer problems through innovative enhancements to product architecture/ micro-architecture


  • BS with 12+ years exp. MS with 8+ years exp or PhD  with 5+ years exp in electrical engineering or computer engineering or related equivalent 
  • Eexperience in the area of designing scalable interconnect / DSP / vector processors, SIMD,  etc.
  • Strong experience in RTL design, verification, and general logic design concepts
  • Experience in designing and developing  SoC/CPU/Interconnect protocol designs 
  • Strong foundation in SoC micro-architecture, design, verification and physical implementation, and ability to influence architecture
  • Understanding of compilers and tools for vector processors
  • Strong analytical problem solving, and attention to details
  • Knowledge of machine-learning, wireless, or data-center infrastructure domains is a plus
  • Expertise in Verilog/System Verilog, C/C++/SystemC, UVM, scripting languages like Perl/Python, etc.
  • Excellent written and verbal communication skills
  • Excellent interpersonal skills, self-motivated  

#DG

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