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Verification Engineer

157749
San Jose, CA, United States
Aug 21, 2019

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Job Description

Description

 

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

Job Description:

 

We are looking for a Verification Engineer to verify high speed SerDes designs.


The individual will help design, develop and use simulation and verification environments, at block and full chip FPGA level, to prove the functional correctness of SerDes designs. Candidate is expected to be a strong team player with good communication skills and the motivation to excel.

 

The individual will have the following responsibilities:

  • Review design document and develop verification strategies for SerDes designs.
  • Develop verification plans and create block and chip level verification environments.
  • Create testcases to meet functional and code coverage goals
  • Debug failures in simulation and collaborate with designers in root-causing failures
  • Investigate methods to improve analog mixed signal behavioral modeling for functional verification.

 #mh


Qualifications:

  • Requires BS with 2+ yrs or MS in Electrical Engineering, Computer Engineering or Computer Science or related equivalent.
  • Requires experience with testbench development using verilog, systemverilog and UVM, 
  • Requires good OOP programming skills in languages such as C++, Python, Java or Systemverilog.
  • Requires good understanding of logic design and digital circuit fundamentals.
  • Coursework with strong performance or experience with DSP and Communication Systems is a big plus.
  • Coursework or experience in analog and/or mixed signal circuit design.

 

 


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