Xilinx Hyderabad is looking for a self-motivated C++ developer to work on an exciting new project which involves giving feedback to the user on timing closure. The ideal candidate has a deep background in timing closure in FPGA synthesis, placement or routing. We are looking for smart, creative people who have a passion for solving complex problems.
The ideal candidate has a strong background in algorithms, data structures and SW engineering, with strong foundations in C++, boost / STL and strong coding practices. The candidate should have a solid understanding of SW quality and processes.
· BS or MS in CS, EE or CE with 3+ years of software development experience
· Background in EDA tools development preferred
· Strong background in computer algorithms and data structures.
· Strong background in C++ programming, including familiarity with boost and STL or Strong background in python programming, including familiarity with numpy and pandas
· Excellent problem solving skills and willingness to think outside the box
· Experience with production software quality assurance practices, methodologies and procedures
· Excellent communication skills and experience working with global teams
Preferred: Exposure to any of these areas:
· RTL Synthesis, datapath or high-level synthesis, technology mapping
· Placement and/or routing algorithms
· Static timing analysis
· FPGAs and the FPGA software tool chain
· Verilog or VHDL
· Scripting languages such as Perl or Python
· Machine learning, data analysis, pattern matching