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Design Engineer II

157438
Singapore, Singapore, Singapore
Sep 24, 2019

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!

 

As part of Wired Engineering

Work on RTL to GDS, including synthesis, placement, clock tree insertion and routing. Also responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc. Work closely with other groups like Analog Design, Systems, Applications and Production in determining architecture and specification of the products.

Bachelor/Masters Degree in Electrical/Computer Engineering

Minimum 3 to 8 years of relevant experience

Good experience and knowledge in design flow from  Netlist to GDS, Floor Plan, Synthesis, route , STA, CTS, RC Extraction and correlation

Static timing analysis, power and noise analysis and back-end verification across multiple projects.

Proficient with backend design EDA tools Synopsys (preferred) or Cadence

Successfully track records of taping out complex SOC

Working knowledge of deep sub-micron routing issues as they relate to power and timing.

Proficient in using Perl and TCL

Self-motivated team worker, good verbal and written communication skills

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