DescriptionXilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).
Senior Design Engineer.
Xilinx is looking for a talented individual to join the design group in the position of Design Engineer to work towards the development of high speed memory controller designs (operating above 6.4 GHz data rate). This person will possess a deep knowledge in system level challenges, logic design and strong experience architecting complex high speed IP’s.
The successful candidate will work as a contributing member and responsible for the architecture and design of next generation memory interfaces for Xilinx customers. Responsibilities include resolving system level challenges, architecting, implementing, documenting and validating the memory controller IP cores. The area of focus would be on high speed memory interfaces like DDR5, LPDDR5 DDR4, LPDDR4, and RLDRAM3. The candidate must have excellent inter-personal and communication skills and be able to work independently.
Xilinx holds a strong position in the FPGA all programmable paradigm. This position offers candidates exposure to the latest generation IP, tools, boards, FPGA products and the ability to design and develop high speed memory IP cores.
B.E/M.E/M.Tech or B.S/M.S in EE/CE with 5+ years of relevant experience.
5+ years of experience in memory controller design such as DDR4/3 or LPDDR4/3 or QDRII+/IV or RLDRAM.
Requires proven track record in technical leadership of teams with 3+ engineers.
Excellent Verilog and logic design concepts.
Working knowledge of C; embedded experience with MicroBlaze preferred
Hands-on experience with lab equipment including logic analyzers and high speed oscilloscopes
Working knowledge of signal integrity methods
Knowledge of bus protocols like AXI/AHB.
Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, and ModelSim.
Excellent communication and problem solving skills.
Should have experience working in geographically dispersed team and should be a strong team player.