DescriptionXilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).
The candidate will be responsible for different design stages in the RTL to GDS implementation.
The candidate will design, implementation RTL for complex digital and analog blocks using Verilog/System Verilog.
The candidate will be responsible for physical design flows (synthesis with DFT, place and route) and work on Static Timing Analysis.
The candidate will work closely with Functional Verification teams to support block level verification (constrained-random and/or directed verification environments using System Verilog and UVM).
The candidate is expected to have strong scripting skills in Perl, Tcl, Shell and/or other languages to support existing & develop new design automation tools/flows for the varied aspects of the design implementation.
The candidate is expected to work with various design groups across different disciplines in different geographical locations.
The candidate is expected to have regular communication with project teams worldwide to resolve issues and ensure targeted goals.
BS with 5+ or MS with 3+ or PhD in Electrical Engineering, Computer Engineering or related equivalent
RTL design implementation of Digital/Analog blocks using Verilog/System Verilog.
Knowledge in VLSI design, Design Automation, IC design.
Knowledge of Physical Design (floor planning, synthesis, place & route) and Static Timing Analysis.
Basic knowledge of EDA Tools (like Synopsys DC Compiler, Primetime, VCS, Cadence Virtuoso).
Experience with UVM/OVM and/or Verilog, System Verilog test benches, BFMs and usage of simulation tools/debug environments is preferred.
Basic understanding of FPGA architecture and customer usage model is a plus.
Knowledge of Cadence SPICE, IC compiler is a plus.
Experience with Silicon debug/validation at the tested and board level is a plus.
Proficiency in Perl, Tcl, Shell, Python and/or other scripting language.
Experience creating internal and/or customer facing detailed documentation.
Excellent written and verbal communication skills in English.
Self-motivated team worker with ability to work in a fast-paced work environment.