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Design Engineer

157302
Hyderabad, India, India
May 30, 2019

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!

 

We are looking for a talented, self-driven and motivated engineer to be part of the Xilinx. In this position you will play a key role in the RTL design of complex & next generation IPs & Systems for the future generations of the Xilinx tools & devices. Responsibilities would include understanding of system requirements, coming up with design specifications, writing RTL and assertions, functional verification, integration with tool flow and also work with Xilinx quality assurance infrastructures to ensure a good quality IP/Sub-System delivery. The key skill requirements are as below:

 

         Strong expertise of using Verilog & System Verilog

         Working knowledge of AXI4 (MM & Stream) interface standards and ARM processors

         Good working knowledge in scripting (like csh, python, tcl)

         Block level verification knowledge, assertions, test plan, test bench and test case creation and exposure to industry standard simulators

         Working knowledge of Xilinx tools and IPs preferred

         Experience in using timing constraints

         Strong issue analysis and on-board debugging skills for FPGA designs

         Self-motivated, organized and process oriented

         Strong verbal & written communication skills

         Experienced in working under global environment

 

Education Requirement

         Bachelors or Masters in Electronics engineering with strong academic background


Years of Experience

4-6 Years

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