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Senior Design Engineer 1

157301
Hyderabad, India, India
Dec 12, 2019

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology.  We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible. 


Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice.  From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world’s first 5G networks, we empower the world’s builders and visionaries whose ideas solve every day problems and enhance people’s lives.


If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you!  At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters – world class technology that improves the way we live and work.  We are ONEXILINX.

 

We are looking for a talented, self-driven and motivated engineer to be part of the Xilinx. In this position you will play a key role in the RTL design of complex & next generation IPs & Systems for the future generations of the Xilinx tools & devices. Responsibilities would include understanding of system requirements, coming up with design specifications, writing RTL and assertions, functional verification, integration with tool flow and also work with Xilinx quality assurance infrastructures to ensure a good quality IP/Sub-System delivery. The key skill requirements are as below:

  • Strong expertise of using Verilog & System Verilog
  • Working knowledge of AXI4 (MM & Stream) interface standards and ARM processors
  • Good working knowledge in scripting (like csh, python, tcl)
  • Block level verification knowledge, assertions, test plan, test bench  
  • Working knowledge of Xilinx tools and IPs preferred
  • Experience in using timing constraints
  • Strong issue analysis and on-board debugging skills for FPGA designs
  • Self-motivated, organized and process oriented
  • Strong verbal & written communication skills
  • Experienced in working under global environment

Education Requirement

  • Bachelors or Masters in Electronics engineering with strong academic background

Years of Experience

  • 4-6 Years

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