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Senior Design Engineer 1

157250
Hyderabad, India, India
May 7, 2019

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Job Description

Description

This exciting position in the Xilinx IP Engineering group as the storage domain u-architect and lead designer will provide the individual with an opportunity to demonstrate strong technical leadership in Xilinx next generation data center storage IP offerings. Join us in delivering innovative IP solutions as we embark on our journey in providing world class storage solutions at more than 100Gbps line rate for Xilinx All Programmable FPGA platforms

As a Senior Design Engineer you will work as part of a team responsible for all phases of product development from definition to execution and Productization. Senior Design engineers are expected to participate in and lead all aspects of a technical project including: working closely with Product marketing managers, u-Architecture development for individual IPs or IP subsystems, leading cross-functional IP teams from front-end development through Productization

This position requires the individual to be creative, team-oriented, technology savvy, able to u-architect and lead complex designs given a high level architecture and take complete responsibility for a quality delivery of the designs

Essential Functions:

A major part of your responsibility will be to take a lead technical role in all phases of the product development cycle from architecture through implementation, prototyping, validation and support including:

·        Evaluating high level architecture to a implementation feasibility level

·        Be the main liaison from the IP engineering team to the high speed IO design team and be the local high speed link design expert

·        Contribute to new process improvement in design and development methodologies that impact the productivity

·        Evaluating and executing design and development plans for IPs

·        u-Architecture, design, documentation, prototyping

·        Working with cross functional teams in reviewing the verification and validation plans and ensure the product delivered is of high quality

 

 

Requirements:

 

•	B.E/M.E/M.Tech or B.S/M.S in EE/ECE with at least 8+ years of relevant experience in IP design
•	Proven end to end design of complex IP using Verilog
•	Strong understanding and experience in design of PCIe, NVMe, RoCE, Ethernet protocols and IEEE 802.3 standards
•	Strong domain knowledge of interfaces which include AXI streaming and high Speed serial connectivity etc
•	Proficient knowledge of Verilog, HDL based methodology and hands on scripting experience for automation
•	Strong knowledge of digital electronics and digital systems
•	Strong debugging skills
•	Knowledge of FPGA architecture and working experience with Xilinx Implementation tools is an added advantage
•	Having System level knowledge / Validating IP at system level and prior working knowledge of the Xilinx implementation tools will be a definite plus 
•	Should have handled design and validation of complex RTL designs on board
•	Self-driven, motivated, result oriented individual with superior academic achievements 
•	Excellent interpersonal, written, group communication and problem solving  skills 
•	Good organizational and execution skills with ability to multi-task and prioritize
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