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Senior Design Engineer

157162
San Jose, CA, United States
Apr 18, 2019

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Job Description

Description

Oversee verification and documentation for application-specific integrated circuit

 (ASIC) and FPGA chip development. Perform verification execution on Memory

 Controllers (DDR, LPDDR, RLDRAM, QDR, HBM) high performance IPs and/or

 SOC designs. Architect verification infrastructure and environments for high

 performance Memory Controllers. Develop and review verification plans. Drive

 successful verification execution for Memory Controllers. Use simulation and/or

 formal based verification environments, at block and full chip FPGA level, to prove

 the functional correctness of DDR (Double Data Rate), LPDDR (Low-Power DDR),

 Reduced-Latency DRAM (RLDRAM), QDR (Quad Data Rate), and HBM (High

 Bandwidth Memory) Memory Controller IP designs.

Special Requirements:    Must have at least 1 year of prior work experience in each of the following:


1. Development of System Verilog based verification environment using UVM (Universal Verification Methodology).

2.  Simulation tools and debug environments using industry standard simulators.

3.  Verification planning, implementation, regression, coverage analysis, data management, and revision control.
4.  Memory Controller standards and protocols.

Education Required: Master’s degree or foreign equivalent in Electrical

Engineering, Computer Engineering, Computer Science, or related field


Experience Required: 3 years of experience as a Verification Architect, Project

Lead, or related occupation


Alternate requirements: Will also accept Bachelor’s degree or foreign equivalent

 in Electrical Engineering, Computer Engineering, Computer Science, or related

 field and 5 years of progressive experience as Verification Architect, Project

 Lead, or related occupation

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