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Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world’s first 5G networks, we empower the world’s builders and visionaries whose ideas solve every day problems and enhance people’s lives.
If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters – world class technology that improves the way we live and work. We are ONEXILINX.
Xilinx is looking for a Staff CAD Engineer (Static Timing Analysis) in the IC CAD Team for the Central Engineering Group to support the design teams.
- BS with 8+ yrs exp, MS with 6+ yrs exp or PhD with 3+
years of exp in Electrical Engineer, Computer Engineering or related
- Proficiency in Perl and Tcl scripting is mandatory.
Prior background in developing EDA software is a plus
- Expertise in Static Timing tools (for example:
PrimeTime) is required
- Experience in design methodologies with multi-voltage
- Good understanding of STA concepts like crosstalk,
- Experience in debugging STA issues related to parasitic
extraction and back-annotation
- Prefer prior experience in developing efficient PrimeTime
- Strong debugging skills. Ability to identify the root
cause of issues and recommend fixes.
- A good understanding of timing constraints, libraries
- Good verbal and written communication skills with the
ability to work with team members across multiple sites