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Design Engineer for Machine Learning Applications

156988
San Jose, CA, United States
Jun 26, 2019

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology.  We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

 

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice.  From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world’s first 5G networks, we empower the world’s builders and visionaries whose ideas solve every day problems and enhance people’s lives.

 

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you!  At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters – world class technology that improves the way we live and work.  We are ONEXILINX.

 

Xilinx is seeking an FPGA design engineer to join our R&D team developing solutions for machine learning and Data Center acceleration. This is an opportunity to be on the ground-floor for the development of new hardware and software technology for accelerating data center workloads with a focus in particular on machine learning.

 

This role has an emphasis on the design and RTL coding of machine learning technology for the Xilinx next generation 7nm Versal platform.

   

Experience: 

  • Experience with the design and RTL implementation of high-performance datapaths for FPGAs is core to the role.
  • FPGA design flows, timing closure, working with DDR memory, RTL coding, Vivado and in general design and verification methodologies for complex performance-optimized FPGA designs are central to this position. A strong knowledge of Python scripting and C coding is very beneficial. 

  • Experience implementing digital signal processing algorithms, for example linear algebra functions, FFTs and other arithmetic functions in hardware is highly beneficial.

 

 
Skills – This candidate would have skills in several, but not necessarily all, of the following
  • Digital design
  • FPGA design flow
  • Verilog, System Verilog
  • Verification methodologies
  • Simulation using Questa, Vivado simulator and other simulators
  • Scripting languages such as python and tcl
  • Knowledge of machine learning datapath architecture would be beneficial
  • C/C++ programming skills would be beneficial

Education: 

  • MS in EE/CE + 6 years of experience;  PhD preferred

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