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Roles and Responsibilities:
- This exiting role will be involved in developing IPs related to computer vision using Vivado High-Level-Synthesis (HLS).
- Individual must be able to understand the CV algorithm(s) and implement it using Vivado HLS targeting for Xilinx FPGA.
- Individual must work effectively with Director and Senior Director level employees within the function, across functions and with external parties.
- To be successful, this individual must demonstrate favorable results through leadership and influencing multiple individuals and groups.
Skills / Experience:
- Experience in C/C++ programming is essential.
- Basic understanding of digital design concepts is required.
- Experience with OpenVX, OpenCL, OpenCV is required.
- Experience with GPU architecture/computing using GPU-accelerated library is a plus.
- Experience with pipeline based architectures/designs is required.
- Experience with RAM based architectures/designs is required.
- Experience in RTL Coding/Simulation using System Verilog/Verilog/System C is a plus.
- Experience in Static timing analysis is a plus.
- Domain knowledge in Computer Vision is required.
- Experience in scripting using Perl, TCL, Shell, Make and/or other scripting languages is required.
- Experience with FPGA flow is a plus.
- Familiarity with Xilinx tools is a plus.
- Strong debug skills are required.
- Strong oral and written communication skills are essential.
- Ability to work collaboratively with other engineers and have strong influencing and leadership skills.
- Ability to effectively communicate with customers about existing and new product directions and technology.
- Ph.D. in Electrical/Electronics/Computer Science engineering.
- Master’s or equivalent degree in Electrical/Electronics/Computer Science engineering with 7+ years of industry experience is required.
- Bachelor’s or equivalent degree in Electrical/Electronics/Computer Science engineering with 8+ years of industry experience is required.