At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.
Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world’s first 5G networks, we empower the world’s builders and visionaries whose ideas solve every day problems and enhance people’s lives.
If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters – world class technology that improves the way we live and work. We are ONEXILINX.
Roles and Responsibilities:
This exiting role will be involved in developing IPs related to computer vision using Vivado High-Level-Synthesis (HLS).
Individual must be able to understand the CV algorithm(s) and implement it using Vivado HLS targeting for Xilinx FPGA.
- Experience in C/C++ programming is essential.
- Basic understanding of digital design concepts is required.
- Experience with OpenVX, OpenCL, OpenCV is a plus.
- Experience with GPU architecture/computing using GPU-accelerated library is a plus.
- Experience with pipeline based architectures/designs is a plus.
- Experience with RAM based architectures/designs is a plus.
- Experience in RTL Coding/Simulation using System Verilog/Verilog/System C is a plus.
- Experience in Static timing analysis is a plus.
- Domain knowledge in Computer Vision is a plus.
- Experience in scripting using Perl, TCL, Shell, Make and/or other scripting languages is a plus.
- Experience with FPGA flow is a plus.
- Familiarity with Xilinx tools is a plus.
- Strong debug skills are required.
- Strong oral and written communication skills are essential
- Master’s or equivalent degree in Electrical/Electronics/Computer Science engineering with 1+ years of industry experience.
- Bachelor’s or equivalent degree in Electrical/Electronics/Computer Science engineering with 2+ years of industry experience.