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Board Layout Design Engineer

156896
San Jose, CA, United States
Apr 1, 2019

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!


Board Layout Design Engineer

We are looking for a talented, self-driven and motivated Senior Board Layout Design Engineer with a strong experience in layout design of analog/RF/high speed digital design boards to join the Board Development team in San Jose, CA.  You will be involved in the layout of high performance, complex boards for some of the most advanced applications in 5G Wireless/IoT/AI/Machine Learning. You will have an opportunity to work in a positive environment where individual development goals are aligned with organizational goals in developing products for some of the life changing and futuristic applications. 

 

Responsibilities:    

  • Responsible for PCB board layout using Cadence Allegro layout tools
  • Responsible for coordinating with SI/PI team, HW Design team, NPI team, and various other teams for completing the board layout and for releasing the board files to manufacturing
  • Work with multiple teams distributed globally 
  • Responsible for all aspects of board design including DFM/DFT/DFA and documentation of designs
  • Responsible for preparation of and implementing checklists for layout and design release

 

 

 

Qualifications:

  • Bachelor’s Degree in Electrical/Computer Engineering;
  • 8-10 years of layout design experience in Analog, RF and HSDD boards
  • Excellent experience in routing of interfaces like PCIe Gen3/4, Multi Gigabit serial buses, DDR4/LPDDR4, Flash, SPI, I2C and switching power supplies
  • Excellent hands-on knowledge of Cadence Allegro PCB design, auto router, Venture, Symphony,  serial and high speed options, HDI, etc..
  • Excellent experience in routing with DFM/DFT/DFA constraints and entering constraints into Constraint Manager.
  • Excellent knowledge of IPC standards, HDI, back drilling, stackup selection, constraint manager
  • Proven experience in designing boards for high volume production, optimizing for reduced number of layers, and cost
  • Excellent written and oral communication skills
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