Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).
This job opening is in the RTL Synthesis team which is part of FPGA Implementation software (FIS) group. FIS group is responsible for delivering state of the art synthesis, optimization, place and route technology for all Xilinx users. We are passionate about extending our leadership position through rapid innovation while maintaining high quality. The team comprises a set of highly skilled engineers who value innovation, quality and team spirit.
In this position, you are responsible for :
- Developing and maintaining best in class HDL compilers, Data flow optimizations and Logic Synthesis algorithms and flows
- Implementing and enhancing Xilinx FPGA specific optimization and mapping flows
- Interacting with IP development and delivery groups, advanced flow groups, Hardware architecture group, GUI group, application architects, and other EDA groups
Education and Experience Requirements
- BS in CS, EE, CE with 7+ years of relevant working experience, MS with 5+ years or related Ph.D. with 2+ years of experience in software industry.
- Proven experience in developing state of the art in one or more of the following areas: HDL compilers, data flow graph optimizations, logic optimization and technology mapping algorithms for ASIC or FPGA synthesis tools is desirable.
- Hands on experience in working with standard data structures like BDDs, SAT solvers and timing analysis engines is desirable.
- Strong background in basic digital design principles, graph theory and data structures required.
- Familiarity with FPGA architectures and flows desirable.
- Fluent in C, C++, Unix shell scripts, Tcl and exposure to using Verilog/VHDL simulators and formal verification tools.
- Experience in developing and supporting large-scale software, including understanding usage model, writing functional specification, implementing code, testing, documentation, and providing customer support.
- Strong communication skills required. Ability to lead and coordinate discussions as well as making presentations in meetings.