Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).
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FDST Verification group is looking for Senior Design Verification Engineer to provide technical leadership, contribution on FPGA block, sub-system and full chip verification. The individual will help design, develop and use simulation and/or formal based verification environments, at block, sub system and full chip FPGA level, to prove the functional correctness of FPGA SoCs. The ideal candidate is one who has a proven track record on driving strategies and successful verification execution on high performance IPs and/or SoC designs. Candidate is expected to be a strong team player with good communication and leadership skills and one who is able to positively and strategically influence the FPGA design teams with an eye towards improving overall product quality.
- Bachelor's Degree w/ 5+ years or MS w/ 3+ years or PhD w/ 1+ years in Electrical Engineering, Computer Engineering, or Computer Science.
- Requires proven track record in technical leadership. This includes planning, execution, tracking, verification closure, and delivery to programs.
- Requires strong experience with development of UVM, OVM, VMM and/or Verilog, SystemVerilog test benches for full chip testbench and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test full chip FPGA fabric and SoCs.
- Requires strong understanding of state of the art of verification techniques, including assertion and metric-driven verification.
- Verification experience in MathEngine/DSP optimized for wireless applications, AXI, NoC, HBM, DDR4, PCIe verification is a plus.
- Verification experience in full chip verification is a plus.
- Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus.
- Strong understanding of different phases of ASIC and/or full custom chip development is required.
- Experience in modeling SystemC and using SystemC based models in verification is a plus.
- Experience with FPGA programming and software is a plus.
- Verification experience in PCIe, Processors, Graphics is a plus.
- Experience with formal property checking tools such as Cadence (IEV), Jasper, and Synopsys (Magellan) is a plus.
- Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.
- Some DFX/DFT and UPF/ power-ware - simulation experience is a plus.