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Senior Design Engineer2

156468
Hyderabad, India, India
Apr 8, 2019

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).


Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!


Xilinx is looking for a talented, self-driven and motivated design engineer to be part of the SDx Application Development team for High Performance Computing. SDx is Xilinx’s primary software user focused IDE. It is built to accelerate the design and development for Xilinx’s devices. The individual will focus on designing and developing applications for the SDx tools. These applications are key part of data center customer.


As a member of this high-performance team, the selected candidate will be responsible for accelerating and implementing FPGA applications. The candidate will understand the C based high level synthesis paradigm and its usage in targeting Xilinx devices. The candidate will also understand parallel programming paradigms like OpenCL and CUDA. The candidate will do application profiling, identifying software code that is a good fit for acceleration on programmable logic and then re targeting those functions using the SDx tools. The candidate will have opportunity to work on both data center and/or embedded domain.


The team provides a fast-paced, start-up like environment offering each individual immense opportunity to interact with a wide variety of people including from other organizations, and truly learn and grow their skills and capabilities. The candidate will have opportunity to interact with Xilinx field engineers and marketing team to understand variety of customer scenario and propose solutions. The candidate will also work closely with SDx development team to understand various features, give suggestions from customer perspective, and help prioritize features.


Qualification:


  • A minimum of Bachelors in EE, CS, CE with 6-10 years of relevant work experience.
    • Strong background either in High Level Synthesis, parallel programming language  or RTL (Verilog/VHDL) Design.
    • Strong programming experience in C/C++ is required.
    • Experience in running, debugging and profiling programs on real HW board is a big advantage.
    • Experience in doing performance profiling of application, functional and memory debugging is required.
    • Must have basic experience in of the scripting language like shell script, perl or python.
    • Must have experience in Linux based development and debug.
    • Exposure to Digital Circuit design or parallel programming paradigm like OpenMP is an advantage.
    • General awareness of ASIC or FPGA design flow including synthesis, place and route is a big advantage.
    • Be able to excel in team environment.
    • Demonstrated ability to identified technical problem, propose viable solutions, and apply technical solutions. 


    Education Requirements :

    A minimum of Bachelors in EE, CS, CE with 6-10 years of relevant work experience.

    Strong background either in High Level Synthesis, parallel programming language  or RTL (Verilog/VHDL) Design.
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