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Architecture Engineer Intern

156453
San Jose, CA, United States
Jan 14, 2019

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI). 

The Xilinx SoC Architecture group is seeking a dynamic architecture engineer (intern), based in San Jose, CA. The candidate will be involved in SoC architecture, performance benchmarking, and/or architectural tradeoff analysis. This is an ideal position for a would-be engineer with a keen interest in computer architecture and system-on-chip (SoC).

 

Job Description includes:

 

  • Analysis of SoC architecture
  • Architectural tradeoffs analysis
  • Performance benchmarking

 

Job Requirements:

 

  • MS or PhD in EE, Computer Engineering or equivalent field
  • Strong analytical problem solving, and attention to details
  • Knowledge of C/C++ , and Python/Perl programming is
  • Knowledge of Linux and CPU benchmarks is desirable
  • Knowledge of Processor and/or SoC architecture
  • Knowledge of HW design, verification, and general logic design & debug concepts is a plus
  • Knowledge of FPGA architectures is a plus
  • Good written and verbal communication,
  • Team work skills

Education Requirements

- Pursuing MS or PhD in EE, Computer Engineering or equivalent field

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