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ASIC Design Engineer

156372
San Jose, CA, United States
Dec 20, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!

 

Xilinx is seeking an ASIC/SOC design engineer to participate in development of next generation high-performance, low-power processor engines for accelerating machine learning/artificial intelligence applications. As part of the front-end design team, you will be involved in microarchitecture design, RTL implementation, analysis and optimization of power/performance, development of timing constraints/SDC, and design checks with Lint/CDC/RDC/DFT DRC tools. You will work closely with architecture, verification/validation, physical design teams to ensure successful IP delivery throughout the complete cycle of design, implementation, and silicon bringup.

  • BSEE with 2 years of experience, or MSEE or equivalent
  • Complete knowledge of basic digital design principles
  • Experience with RTL design in Verilog/SystemVerilog
  • Understanding of ASIC or FPGA design flows
  • Experience with design within timing and power constraints

  • Experience in following is desired:
    • Understanding of FPGA architecture and implementation flow
    • TCL, Perl, Python scripting
    • Simulation environment such as VCS, Questa
    • Synopsys DesignCompiler
    • Version control systems such as Perforce, ICManage or Git
  • Good communication (verbal and written) and presentation skills
  • Good organization and self-starter

 

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