Xilinx develops highly flexible and adaptive processing
platforms that enable rapid innovation across a variety of technologies - from
the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA,
hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration
Platform), designed to deliver the most dynamic processor technology in the
industry and enable the adaptable, intelligent and connected world of the future
in a multitude of markets including Data Center (Compute, Storage and
Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation
& Prototyping; Aerospace & Defense; Industrial Scientific & Medical,
and others. Xilinx's core strengths simultaneously address major industry trends
including the explosion of data, heterogeneous computing after Moore's Law, and
the dawn of artificial intelligence (AI).
Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!
Detailed description :
This exciting position in the Xilinx IP Engineering group as the connectivity IO team u-architect and lead designer will provide the individual with an opportunity to demonstrate strong technical leadership in Xilinx next generation IP solutions. Join us in providing innovative IP solutions as we embark on our journey in providing world class IP solutions running on Xilinx All Programmable FPGA platforms
As a Staff Engineer you will work as part of a team responsible for all phases of product development from definition to execution and Productization. Staff Design engineers are expected to participate in and lead all aspects of technical projects including: new product exploration, evaluating emerging technologies, working closely with Product marketing managers and end customers, u-Architecture development for individual IPs or IP subsystems, leading cross-functional IP teams from front-end development through Productization
- Strong oral and written communication skills are essential
- Ability to work collaboratively with other engineers and have strong influencing and leadership skills
- Detailed understanding and proven track record of developing leading edge standard and proprietary high speed interfaces like PCIe, Ethernet
- Good understanding of system design aspects and its impact on performance and throughput
- Experience in system level validation and debug of system solutions
- Familiarity with electrical challenges that come with high speed link design
- Detailed knowledge of networking and Ethernet protocols is a plus
- Experience with high speed link designs above 10Gbps line rate is a plus
- The ideal candidate will be a proactive contributor and subject matter expert
- Ability to effectively communicate with customers about existing and new product directions and technology.
- Individual must work effectively with Director and Senior Director level employees within the function, across functions and with external parties.
- To be successful, this individual must demonstrate favorable results through leadership and influencing multiple individuals and groups.
- Contributes, explicitly or by example, to the standards and processes used by Xilinx or product development.