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Serdes PHY Design Engineer

156267
San Jose, CA, United States
Dec 4, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Xilinx Serdes Technology Group develops high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS process. We are currently seeking a serdes physical layer (PHY) design engineer to join our world-class team.

 

Responsibilities: 

  • Circuit design of wireline transceiver building blocks (PLL, clock distribution, receiver front-end, transmitter front-end, serializer, deserializer, etc.
  • Working with validation team to evaluate silicon results

Qualifications:

  • M.S in Electrical Engineering with relevant project/internship experience
  • Strong background in analog circuit design as demonstrated through course work design project, internship, or work experience.
  • Strong teamwork and communication skills

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