DescriptionXilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).
The Serial Transceiver Group team designs high speed serial interface systems which are integrated into FPGA devices. These devices are used in a variety of applications such as automotive, wireline and wireless communications. Successful physical implementation of these serial communications solutions requires an advanced knowledge of mixed signal layout techniques.
Successful candidates will work as part of an experienced team executing projects in advanced CMOS manufacturing processes. Layout is extremely challenging at these smaller process nodes. Project tasks will include: layout of analog and digital circuits. There is the opportunity to contribute to methodology initiatives to accelerate design layout.
• Design complex layout for mixed signal, and analog circuits. (including block level and chip level layout)
• Review and analysing floor plans and complex circuits with circuit designer.
• Run a complete set of design verifications.
• Collaborate with the circuit design team to plan, and schedule work and negotiate any necessary layout tradeoffs as needed.
• Utilize advanced CAD tools, mask design knowledge to layout correct and robust physical design representation of circuits.
• Ability to work independently as well as in teams, including remote design teams
• BSEE preferred, at least three (3+) years of custom or analog IC physical design experience
• Experience with schematic-driven layout, floor planning, chip level routing, design for manufacturing and design rule and connectivity verification is preferred
• Understanding of cutting edge silicon process technologies (CMOS 28nm and below) and device physics
• Hands-on experience using Cadence Virtuoso XL or GXL is preferred
• Mentor Caliber experience to run DRC & LVS
• Familiarity with analog and digital layout tools and flows, circuit design concepts and IC manufacturing processes
• Understanding of parasitic impact on circuit performance is a plus.
• Capable of top level floor planning with knowledge of transistor, resistor, and capacitor matching in sub-micron process.
• Understanding of digital SOC flow is a plus.
• Team player with good communication and documentation skills.
• Capacity to take on board new approaches and working methods