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SerDes Architect

155995
San Jose, CA, United States
Nov 27, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!

 
The SerDes Architecture and Modeling Group has responsibilities in generating robust SerDes architecture and algorithms, creating silicon and system level specifications, developing and verifying SerDes design models, developing IBIS-AMI models for system level simulations and for customers, evaluating system performance margin trade-offs, analyzing system SI and PI, and bringing up and characterizing silicon.

We’re looking for a system architect to join a fast paced transceiver design team. Our team stays ahead of the technology curve to deliver world-class programmable transceiver solutions for multiple FPGA platforms, supporting over 20 protocols with thousands of customer applications.

The successful candidate will be analytical, thorough, self-driven, and have an excellent track record in the following areas:
 
  • Signal processing, data coding, and FEC algorithms
  • SerDes architecture development including equalizers and time recovery for NRZ and PAM4 systems
  • Behavioral modeling of different blocks in transceivers
  • Familiarity with optical link analysis and evaluation is a plus
  • Presenting design trade-off analyses and implementation recommendations with custom circuit designers

Qualifications:

  • Master’s Degree in Electrical Engineering or similar technical field   
  • Strong signal modulation, coding, and FEC knowledge and experience
  • Demonstrated experience with using and developing transceiver modeling, analysis, and characterization tools – IBIS-AMI model development experience is a plus and familiarity with Simulink/Matlab and C/C++ programming
  • Hands on architecture experience with transceiver equalizers (TX FIR, RX analog FFE, CTLE, and DFE) – DSP (FFE and DFE) experience is preferred
  • Architecture experience with transceiver timing recovery, such as high speed PLLs, CDRs, etc.
  • ADC based SerDes architecture experience is a plus
  • Experience with lab equipment for high-speed digital systems
  • Good understanding of high speed signal integrity issues
  • Excellent technical communication skills (presentations and documentation)
  • Team player
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