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Software Engineer, HDL Simulation

155990
Longmont, CO, United States
Nov 14, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!

 

Xilinx is seeking a talented, motivated and self-driven software engineer to be part of the Xilinx Simulation, Debug and Profiling team. The selected candidate will get opportunity to work on developing cutting edge debugging and profiling features in newly being developed SDx tool chain which is meant to allow application developers with little or no FPGA expertise to use high level programming languages such as OpenCL, C and C++ to program FPGAs.

 

Additionally, the candidate will be responsible for developing and improving a wide variety of features in the Xilinx simulator’s object code-generating HDL (Hardware Description Language such as Verilog, VHDL, and SystemVerilog) compilers, simulation kernel, and user interface logic that supplies data for the simulator’s GUI.

Qualifications:

 

  • Bachelor's Degree in Computer Science, Computer Engineering or related fields, Data structures and algorithms, C/C++ programming plus 2 years of experience or a Master's Degree in Computer Science, Computer Engineering or related fields
  • Prior coursework or experience in one or more of FPGA programming, Profiling software or hardware, building debuggers, developing compilers
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