UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Senior Physical Design Engineer

155978
San Jose, CA, United States
Oct 19, 2018

Share:

Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).
 
Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!
 
Design and implement digital integrated circuits blocks for Xilinx's next generation FPGAs on industry leading CMOS technologies. Participate in architecture definition, block specification, and floor planning. Implement design strategies to optimize block-level clocking, signal-flow, and interface management.  Evaluate future product requirements for power, performance and area. Design custom and semicustom circuits for area, performance and power. Perform analog and digital simulation, static timing analysis, and silicon and electrical rule verification.  Debug issues identified post-tape out and perform root-cause analysis based on implementation and design knowledge.
 
Responsibilities:
  • Work with RTL designers to define and review critical design constraints for functionality, performance, power, and area
  • Identify key areas of pre-silicon analysis that need to be completed and guide junior engineers in performing such analysis.
  • Runs design models through EDA tools to anticipate and address implementation challenges prior to fabrication (i.e., 'pipe clean' tools)
  • Demonstrates a broad understanding of process technology and circuit capability in implementing component design
  • Exercises solid analytical problem solving in troubleshooting component designs (e.g., timing analysis, constraint setting)
  • Develops customization scripts for local optimization
  • Works effectively with evolving tool sets
  • Can properly analyze how all the elements of a design solution fit together
  • Can perform an End to End System performance analysis
  • Can properly evaluate internal and 3rd party IP solutions against requirements
  • Works efficiently and with agility to implement designs (e.g., transistor design, RTL coding, synthesis, conversion, linear dimension work, integration, verification)

#sb

Qualifications:
  • Master’s Degree in Electrical Engineering with 3+ years of industry experience in high speed digital design.
  • Experience with high speed circuit design techniques.
  • Demonstrated experience with Circuit design tools & simulators (i.e., ICC2 ,Primetime, DesignCompiler, Virtuoso, Calibre), Logical Equivalency Checking (Conformal/Formality)
  • Knowledge of DSP fundamentals, techniques, and circuits.
  • Hands on experience with full ASIC design flows and methodologies
    • Experience with standard cell based design and verification
    • Familiarity with static timing analysis tools
  • RTL design using Verilog preferred
  • Scripting language preferred
  • UNIX environment.

#sb

Share:

Similar Jobs

Design Engineering Intern

San Jose, CA, United States

Intern - Software Engineer

San Jose, CA, United States

Serdes PHY Design Intern

San Jose, CA, United States

Serdes PHY Design Intern

San Jose, CA, United States

Serdes PHY Design Intern

San Jose, CA, United States

Serdes PHY Design Intern

San Jose, CA, United States

Administrative Assistant

San Jose, CA, United States

Human Resources Representative

San Jose, CA, United States

System Validation Engineer

San Jose, CA, United States

Sr. Staff FPGA Characterization Engr.

San Jose, CA, United States

Serdes STA Engineer

San Jose, CA, United States

Serdes PHY Design Engineer

San Jose, CA, United States

Embedded Software Engineer

San Jose, CA, United States

Embedded Software Engineer

San Jose, CA, United States

Serdes Analog/Mixed Signal Design Engineer

San Jose, CA, United States

Validation Engineer

San Jose, CA, United States

SerDes Validation Engineer

San Jose, CA, United States

SerDes Architecture and Modeling Engineer

San Jose, CA, United States

Serdes PHY Design Engineer

San Jose, CA, United States

Senior SoC/ASIC Design Verification Engineer

San Jose, CA, United States

IT Merger & Acquisition Director

San Jose, CA, United States