Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).
Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!
the Physical design lead of the MPSoC design team in
Hyderabad, you'll be responsible for leading physical design
closure efforts for complex designs. Taking design from RTL to GDSII. Owning
and driving few aspects of design like synthesis, DFT , timing and physical
Duties , Competencies & Responsibilities include, but not limited to:
a timing signoff team to take a design from RTL to GDSII
on ownership of one or more activities of physical implementation flow
especially focussed on full chip timing signoff
with RTL design, DFT and physical design teams to resolve all resolve
issues for implementation
in design reviews and design closure discussions
or enhance scripts for various physical closure activities
technical mentoring, and knowledge sharing via brown bags, formal
presentations, and working meetings to broad organization and leaders
and drives workflow processes to mitigate challenges and support planning
understanding of complete physical design flow in 16nm, 7nm
have gone through multiple tapeout cycles, revisions and metal ECOs in
ASIC, SOC domains
on Expertise with PD,STA tools (like ICC, Primetime) is a must
be an expert in timing methodologies - STA signoff flows, constraint
creation and verification, clock tree estimation/guidance , budgeting
flows, optimization techniques, hierarchical timing modelling, , ECO
generation, OCV, spice sims etc
in timing convergence performances in processor cores, high speed
interfaces is desired.
- Strong scripting skills
using Perl, TCL, C-shell, Make and/or other scripting languages.
characterization and post silicon timing correlation , critical path simulation, spice clock path simulation
(jitter/duty cycle), repeater and feed-through methodologies is a
verbal and written communication skills.
Course work, research, professional
experience on physical closure, floorplan, CTS, routing, timing,
noise, crosstalk, electro migration, IR drop, process variations,
characterization, 3D ICs, low power cmos, digital logic and circuit
design, ASIC/ SOC integration.
BE. MS Elec or equivalent
Years of Experience