Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).
Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!
Your responsibilities include but are not limited to:
- Block level place and route to design closure meeting timing, area and power constraints.
- Create Block/fullchip metal track plan including power grid.
- Generate and Implement ECOs to fix timing, noise and EM IR violations.
- Run Physical design verification flow at Block / full chip level and provide guidelines to fix LVS/DRC violations to COE owners
- Participate in Methodology/flow development for blocks and at full chip level which include correct by construction designs
- Exploring methodology improvements for better power, performance , area and overall productivity
- Master’s/Bachelor’s degree in Electrical/Electronics engineering with 8 to 14 years of experience in semi-custom or PNR design
- Knowledge of and/or experience with industry standard PNR and layout tools which include Synopsys ICC/ICC2, Cadence Innovus, cadence virtuoso, CalibreDRV etc
- Knowledge of and/or experience with industry standard timing and physical verification tools such as PrimeTime and Calibre
- A good understanding of electrical, timing and reliability issues in deep sub micron circuit design.
- Strong debug skills
- Scripting experience using Perl, TCL, C-shell, Make and/or other scripting languages
- Knowledge and experience with basic Unix data management and job control
- Excellent written and oral communication skills
Master’s/Bachelor’s degree in Electrical/Electronics engineering
Years of Experience
8 to 14 years of experience in PNR design