Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).
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Xilinx FDST Verification group is looking for a Senior Staff Design Verification Engineer to provide technical leadership and contribution on SOC and IP designs. The individual will help design, develop and use simulation and/or formal based verification environments at block, full chip and SOC level to prove the functional correctness of the designs.
- The ideal candidate is one who has a proven track record on driving strategies and successful verification execution on multiple high performance IPs and/or SOC designs.
- Require proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs.
- Candidate is expected to be a strong team player with good communication and leadership skills and one who is able to positively and strategically influence the design teams with an eye towards improving overall product quality.
- Requires BS w/ 12+ yrs or MS 8+ yrs or PhD with 5+ yrs experience in Electrical Engineering, Computer Engineering, Computer Science or related equivalent.
- Require experience with development of UVM/OVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES using multiple VIPs.
- Require strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance IP and/or VLSI designs is a plus.
- Develop and work with different verification platforms in SystemC/System Verilog including utilization of Emulation/Prototyping platforms for verifying next generation multi-core SOC designs.
- Responsible for a comprehensive verification plan and to drive the implementation of verification test cases from applications and other sources.
- Strong foundation in SoC architecture and verification of multi-core processors including SIMD, Vector processors, floating point, etc. is a plus
- Require familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management.
- Experience with FPGA programming and software is a plus.
- Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan / VC Formal) is a plus.
- Experience with mixed-signal verification tools and methodology is a plus.
- Experience with gate level simulation, power verification, reset verification, contention checking is a plus.
- Experience with silicon debug at the tester and board level, is a plus.