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Design Engineering Manager

155892
San Jose, CA, United States
Sep 12, 2018

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Job Description

Description

Xilinx is the world's leading provider of All Programmable FPGAs, SoCs and 3D ICs. These industry-leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration. Our All Programmable devices underpin today's most advanced electronics. Among the broad range of end markets we serve are:

  • Aerospace/Defense
  • Automotive
  • Broadcast
  • Consumer
  • High Performance Computing
  • Industrial / Scientific / Medical (ISM)
  • Wired
  • Wireless

 

Provide technical leadership and managerial direction to projects in FPGA full chip verification development. Design, develop, or test electronic components for ASIC development. Engage in FPGA block, sub-system and full chip verification. Design and develop test cases using simulation and/or formal-based verification environments at block, sub-system and full chip levels, and prove the functional correctness of FPGA SOCs (System on Chip). Drive strategies and successful verification execution on high performance IPs and SOC designs. Plan, execute, track, close verification, and deliver to programs.   Prepare and present reports outlining the future of technical projects and makes recommendations for actions necessary to achieve desired results. Responsible for verifying FPGA full chip designs. Help design, develop, and use simulation and verification environments, at block and full chip FPGA level.


#LI-DNI

Education:
  • Master or foreign equivalent in Electronics Engineering, Electrical Engineering, Computer Engineering, Computer Science, or related field.
Experience:
  • 7 years of progressive experience as Principal IC Design, Sr. Manager Design Verification, Electrical Sr. Staff Engineer or related occupation.
Alternate Requirements:
  • Will also accept Bachelor’s degree or foreign equivalent in Electronics Engineering, Electrical Engineering, Computer Engineering, Computer Science, or related field plus 9 years progressive experience in position or related occupation.
Special Requirements:
  • Must have at least 1 year of prior work experience in each of the following: 
    1. Project management, planning, estimation and scheduling.
    2. Architect and implement verification environment using verification methodology including UVM or SystemVerilog.
    3. Test plan development and test writing.
    4. Analyzing and debugging failures using simulation tools including Synopsys VCS or DVE to verify hard IPs, FPGA fabric or System-on-Chip.
    5. Functional coverage writing, coverage collection and analysis, coverage closure.
    6. Writing System Verilog assertions and assertion based verification.
#LI-DNI
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