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SOC Design Intern

155873
San Jose, CA, United States
Nov 30, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI). 

 

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!

 

We have an opening for a Digital Hardware Design Intern in the SOC Design team.

In this role, you will work closely with SOC Design/Integration team, SOC Verification and Emulation teams to contribute to development, verification and maintenance of some sub-blocks of the SOC.

Required

Undergrad completing Senior year in BSEE or MSEE Student completing final year

Looking for someone to start in November 2018

Good understanding of Verilog, SystemVerilog, and Digital Design principles

Experience with automation using scripting techniques such as PERL, Python and TCL

FPGA knowledge and emulation

Experience with industry-standard EDA tools from Cadence, Synopsys or Mentor

Digital Design experience

Experience with building block level verification suites

Excellent verbal and written communication skills

Ability to develop clear and concise engineering documentation

 

Desired

Hands on experience of Front End Design and Implementation steps including Micro-Architecture, RTL Coding, constraints generation/verification/review, Lint check, CDC check, DC Synthesis and PT Static Timing Analysis.

Understanding of DFT insertion techniques including SCAN, ATPG, MBIST and LBIST

Understanding of AMBA protocols such as AXI, APB, ACE and AHB

Excellent organizational skills and attention to detail

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