Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).
Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!
In this role, candidate would be responsible for analysis, characterization and correlation of chip level power of high performance heterogeneous architecture SoCs.
This person will be a key member of the SoC Design and Systems Engg. Organization and will be responsible for analysis and characterization of the power consumption of the various power domains of high performance SoCs. In addition, the candidate will be responsible for working with different power analysis tools at Xilinx and ensuring correlation between Silicon power and reported power in the tools. In this role, the candidate will
• be working with cross-functional groups (architecture, design, Test, software tools, etc.) to ensure that the low power design of the SoC is fully analyzed, characterized and correlated.
• Define and assist in development of power characterization vectors
• Work with Marketing, Architecture and Design teams for developing and providing power estimation models for the SoC power modes and domains.
• Define and develop System level power use cases that exercise the low power features of next generation SoCs