Mixed Signal Verification Engineer
Xilinx is looking for a talented engineer to join the Analog Mixed Signal verification group which develops complex mixed analog/digital systems in 20nm, 16nm and 7nm process geometries.
The scope of the work includes verification of complex algorithms for “digitally assisted analog” techniques, control and bus interfaces and high speed data interfaces.
The responsibilities include; the development of metric driven verification solutions; working with best in class tools and implementing verification frameworks/environments to verify complex mixed signal designs; collaboration with the digital and analog design teams to deliver the complete verification solution.
- 3+ years industry hands-on experience in ASIC design/verification
- Bachelor/Masters/PhD Degree in Electronic/Computer Engineering
- Strong understanding of, and direct experience in the development of verification environments and methodologies at block and chip level
- Extensive knowledge of SystemVerilog / Verilog / VHDL
- Good problem solving skills and ability to analyse and debug RTL design issues
- Excellent written and oral communication skills
- Ability to work well as part of a team
- Experience with state of the art of verification techniques - constrained random stimulus generation, assertion, functional coverage - and using verification methodologies such as OVM/UVM/VMM
- Good understanding of Object-Oriented programming concepts
- Experience with one or more scripting languages - Python, Perl, TCL/TK, Shell scripting
- Good understanding of Digital Signal Processing
- Matlab/Octave experience would be beneficial